Product Summary
The 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HCT373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.
Parametrics
74HCT373 absolute maximum ratings: (1)VCC, supply voltage: -0.5 to +7 V; (2)IIK, input clamping current: ±20 mA max when VI < -0.5 V or VI >VCC +0.5 V; (3)IOK, output clamping current: ±20 mA max when VO <-0.5 V or VO >VCC +0.5V; (4)IO, output current: ±35 mA max when VO = -0.5 V to (VCC +0.5V); (5)ICC, supply current: -70 mA max; (6)IGND, ground current: -70 mA max; (7)Tstg, storage temperature: -65 +150℃; (8)Ptot, total power dissipation: 750 mW.
Features
74HCT373 features: (1)3-state non-inverting outputs for bus oriented applications; (2)Common 3-state output enable input; (3)Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573; (4)ESD protection: HBM JESD22-A114F exceeds 2 000 V; MM JESD22-A115-A exceeds 200 V; (5)Specified from -40 to+85℃ and from -40 to+125℃.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
Quantity | |||||||||||||
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74HCT373 |
Other |
Data Sheet |
Negotiable |
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74HCT373D |
NXP Semiconductors |
Latches OCTAL 3-STATE LATCH |
Data Sheet |
Negotiable |
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74HCT373D-T |
NXP Semiconductors |
Latches OCTAL D LATCH 3STATE |
Data Sheet |
Negotiable |
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74HCT373N,652 |
NXP Semiconductors |
Latches OCTAL D LATCH 3STATE |
Data Sheet |
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74HCT373PW |
NXP Semiconductors |
Latches OCTAL 3-STATE LATCH |
Data Sheet |
Negotiable |
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74HCT373PW-T |
NXP Semiconductors |
Latches OCTAL 3-STATE LATCH |
Data Sheet |
Negotiable |
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74HCT373PW,118 |
NXP Semiconductors |
Latches OCTAL 3-STATE LATCH |
Data Sheet |
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74HCT373PW,112 |
NXP Semiconductors |
Latches OCTAL 3-STATE LATCH |
Data Sheet |
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