Product Summary
The EPC2TC32(N) is an FPGA. It allows the user to initiate configuration of the FPGA via an additional pin, nINIT_CONF. The nINIT_CONF pin of the EPC2TC32(N) can be connected to the nCONFIG of the FPGA(s), which allows the INIT_CONF JTAG instruction to initiate FPGA configuration. The INIT_CONF JTAG instruction causes the EPC2TC32(N) to drive nINIT_CONF low, which in turn pulls nCONFIG low. Pulling nCONFIG low on the FPGA will reset the device.
Parametrics
EPC2TC32(N) absolute maximum ratings: (1)Supply voltage:–2.0V to 7.0V; (2)DC input voltage:–2.0V to 7.0V; (3)DC VCC or ground current:50mA; (4)DC output current, per pin:–25mA to 25mA; (5)Power dissipation:250mW; (6)Storage temperature:–65℃ to 150℃; (7)Ambient temperature:–65℃ to 135℃; (8)Junction temperature:135℃.
Features
EPC2TC32(N) features: (1)Easy-to-use 4-pin interface to Altera FPGAs; (2)Low current during configuration and near-zero standby current ; (3)5.0-V and 3.3-V operation; (4)Software design support with the Altera Quartus II and MAX+PLUS II development systems for Windows-based PCs as well as Sun SPARCstation, and HP 9000 Series 700/800; (5)Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers ; (6)Available in compact plastic packages:8-pin plastic dual in-line package (PDIP), 20-pin plastic J-lead chip carrier (PLCC)package, 32-pin plastic thin quad flat pack (TQFP) package; (7)5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface; (8)Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1; (9)ISP circuitry is compatible with IEEE Std. 1532.
Diagrams
EPC2 |
Other |
Data Sheet |
Negotiable |
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EPC2001 |
TRANS GAN 100V 25A BUMPED DIE |
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EPC2007 |
TRANS 100V 30MO BUMPED DIE |
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EPC2010 |
TRANS GAN 200V 12A BUMPED DIE |
Data Sheet |
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EPC2012 |
TRANS GAN 200V 3A BUMPED DIE |
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EPC2014 |
TRANS GAN 40V 10A BUMPED DIE |
Data Sheet |
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