218S6ECLA21FG

Product Summary

The 218S6ECLA21FG is a south bridge that integrates key I/O, communications, and audio features required in a state-of-the-art PC into a single device. The 218S6ECLA21FG is specifically designed to operate with AMD’s families of integrated graphics processors (IGPs) in desktop and mobile PCs.

Parametrics

218S6ECLA21FG absolute maximum ratings: (1)VDD_[12:1]:-0.5V to 1.32V; (2)VDDQ_[28:1]:-0.5V to 3.66V; (3)S5_1.2V_[4:1]:-0.5V to 1.32V; (4)S5_3.3V_[6:1]:-0.5V to 3.66V; (5)AVDDCK_3.3V:-0.5V to 3.66V; (6)AVDDCK_1.2V:-0.5V to 1.32V; (7)PCIE_PVDD:-0.5V to 1.32V; (8)PCIE_VDDR[13:1]:-0.5V to 1.32V ; (9)AVDD_SATA[15:1]:-0.5V to 1.32V; (10)PLLVDD_SATA_[2:1]:-0.5V to 1.32V; (11)XTLVDD_SATA:-0.5V to 1.32V; (12)VBAT:-0.5V to 3.6V BAT; (13)AVDDC:-0.5V to 3.66V; (14)AVDDRX[4:0]:-0.5V to 3.66V; (15)AVDDTX[4:0]:-0.5V to 3.66V; (16)USB_PHY_1.2V[5:1]:-0.5V to 1.32V; (17)V5_VREF:-0.5V to 5.5V; (18)Any 3.3V input signal:-0.5V to 3.66V; (19)Any 3,3V 5V tolerant input signal:-0.5V to VREF+0.5V.

Features

218S6ECLA21FG features: (1)Supports ACPI S1 to S5 ; (2)Supports legacy keyboard/mouse ; (3)Supports USB debug port ; (4)Supports port disable with individual control; (5)Supports IOAPIC/X-IO APIC mode for 24 channels of interrupts ; (6)Supports 8259 legacy mode for 15 interrupts ; (7)Supports programmable level/edge triggering on each channels ; (8)Supports serial interrupt on quiet and continuous modes ; (9)Supports PCI Rev. 2.3 specification ; (10)Supports PCI bus at 33MHz ; (11)Supports up to 6 bus master devices ; (12)Supports 40-bit addressing ; (13)Supports interrupt steering for plug-n-play devices ; (14)Supports concurrent PCI operations ; (15)Supports hiding of PCI devices by BIOS/hardware ; (16)Supports spread spectrum; (17)Supports LPC based super I/O and flash devices ; (18)Supports two master/DMA devices ; (19)Two cascaded 8237 DMA controllers ; (20)Supports PC/PCI DMA ; (21)Supports LPC DMA ; (22)Supports type F DMA; (23)1/2/4-lane A-Link Express II interface ; (24)Dynamic detection of lane configuration ; (25)High data transfer bandwidth.

Diagrams