(China (Mainland))
Product Summary
The 48LC2M32B2-7 is a high-speed CMOS, dynamic random-access memory containing 67,108,864-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). The 48LC2M32B2-7 provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. The 48LC2M32B2-7 uses an internal pipelined architecture to achieve high-speed operation.
Parametrics
48LC2M32B2-7 absolute maximum ratings: (1)Voltage on VDD, VDDQ Supply Relative to VSS: -1V to +4.6V; (2)Voltage on Inputs, NC or I/O Pins Relative to VSS: -1V to +4.6V; (3)Operating Temperature, TA:0℃ to +70℃; (4)Extended Temperature:-40℃ to +85℃; (5)Storage Temperature (plastic):-55℃ to +150℃; (6)Power Dissipation:1W.
Features
48LC2M32B2-7 features: (1)PC100 functionality; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes; (7)Self Refresh Mode; (8)64ms, 4,096-cycle refresh (15.6μs/row); (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ±0.3V power supply; (11)Supports CAS latency of 1, 2, and 3RAM.
Diagrams
